The present invention relates to a digital data demodulating apparatus and, more particularly, to a digital data demodulating apparatus for obtaining a correct sampling timing from a received signal distorted by inter-symbol interference.
As a conventional digital data demodulating apparatus of this type, a demodulating apparatus designed to estimate a channel impulse response from a received signal sequence sampled at a speed twice a symbol speed, and demodulate a sampling phase, which provides the maximum value of power of the estimated channel impulse response value, as a correct sampling phase is known (e.g., Giovanna D'aria, Roberto Piermanrini, and Valerio Zingarelli, "Fast Adaptive Equalizer for Narrow-Band TDMA Mobile Radio", IEEE, Transaction on Vehicular Technology, Vol. 40, No. 2, May, 1991).
A conventional digital data demodulating apparatus will be described below with reference to the accompanying drawings.
FIG. 7 shows a conventional digital data demodulating apparatus.
Referring to FIG. 7, this conventional digital data demodulating apparatus comprises an input terminal 700, a sampling circuit 701 having a sampling speed twice a symbol speed, impulse response estimators 702 and 703, power calculating circuits 704 and 705, a comparator 706, switches (SWs) 707 and 708, an equalization circuit 709, and an output terminal 710.
A received signal sampled by the sampling circuit 701 at a speed twice the symbol speed is regarded as sequences sampled at the same speeds as the symbol speeds of two sequences, and is sent to the impulse response estimators 702 and 703 and the switch (SW) 707. The impulse response estimators 702 and 703 estimate channel impulse responses corresponding to the respective sequences. Upon reception of the outputs from the impulse response estimators 702 and 703, the power calculating circuits 704 and 705 calculate the powers of the estimated channel impulse responses, respectively. The comparator 706 compares the signals from the power calculating circuits 705 and 706 and outputs the comparison result to control the switches (SWs) 707 and 708 so as to demodulate one of the sequences which corresponds to the communication impulse response having a higher power. Upon reception of the outputs from the switches (SWs) 707 and 708, the equalization circuit 709 demodulates the sequence sampled at the symbol speed obtained from the switch (SW) 707 on the basis of the channel impulse response obtained from the switch (SW) 708. Note that the switch 708 receives the outputs from the impulse response estimators 702 and 703 as inputs.
In this conventional digital data demodulating apparatus, when an actual channel impulse response is shorter than a predetermined length, no deterioration in reception characteristics occurs. If, however, the impulse response length is larger than the predetermined length, a deterioration in reception characteristics occurs because no consideration can be given to a residual inter-symbol interference component exceeding the predetermined length.